Field of the Disclosure
The present disclosure relates generally to error detection and correction schemes in processing systems and, more particularly, to error detection and correction schemes for data stored in off-chip memory.
Description of the Related Art
Error detection and correction schemes are utilized in processing systems to detect errors that may occur during the transmission of data. Error detection schemes employ a variety of techniques to ensure data reliability including error-correcting code (ECC) and checksum schemes employing cyclic redundancy checks (CRCs) and parity bits. CRC values are implemented to detect a possible error that has occurred in data accessed from off-chip memory (that is, memory external to the processor), while using parity information accessed from the off-chip memory to correct the detected error. Once corrected, the corrected data value may be written back to the off-chip memory.